ASIC Digital Verification Engineer

Job Summary

Renesas Electronics is seeking an entry‑level ASIC Digital Verification Engineer to join its Ottawa, Ontario office. This full‑time, onsite role offers the chance to work on mixed‑signal Digital PLL ASICs within a growing design and verification team.

Key Responsibilities

• Develop and execute verification plans for mixed‑signal digital PLL ASICs.
• Create testbenches, develop stimulus, and write self‑checking checkers using SystemVerilog/UVM.
• Collaborate with design engineers to identify and resolve functional bugs.
• Maintain verification environment, scripts, and documentation.
• Participate in design reviews, code reviews, and team meetings.
• Contribute to continuous improvement of verification methodologies.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering or related field (up to 2 years experience) or a recent Master’s graduate.
• Fundamental knowledge of digital ASIC design and verification concepts.
• Experience with Verilog/SystemVerilog and simulation tools (e.g., VCS, Questa).
• Familiarity with UVM methodology is a plus.
• Strong analytical and problem‑solving skills.
• Excellent written and verbal communication in English.

What We Offer

• Opportunity to work on industry‑leading mixed‑signal ASIC projects.
• Mentorship from experienced engineers and a collaborative team environment.
• Professional development and training resources.

Frequently Asked Questions

Do I need prior ASIC verification experience?

A bachelor’s degree and up to 2 years of relevant experience or a recent master’s graduate are acceptable; foundational knowledge of verification is required.

Is this position remote or onsite?

The role is 100% onsite at Renesas Electronics’ Ottawa office.

What tools will I use in this role?

You will work with SystemVerilog, UVM, and industry‑standard simulators such as VCS or Questa.