ASIC DFT (Design for Test) Lead

Role: ASIC DFT (Design for Test) Lead Location: Remote Duration: 12 months (possibly extending longer based on project timelines) Candidate Responsibilities: · Responsible for implementing the Hardware Design-for-Test (DFT) features – scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug · Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integratio…