Sr. Software Verification Engineer (Teradyne, North Reading)

Job Summary

Teradyne is seeking a Sr. Software Verification Engineer to join its North Reading, Middlesex County, US team. This senior role focuses on developing and executing verification strategies for cutting‑edge test and automation software.

Key Responsibilities

• Design, implement, and maintain verification plans and testbenches for complex software modules.
• Develop automated test frameworks using Python, C++, and industry‑standard verification languages.
• Collaborate with cross‑functional hardware and firmware teams to define verification requirements.
• Identify, isolate, and track defects; drive root‑cause analysis and resolution.
• Mentor junior engineers and promote best practices in verification methodology.
• Contribute to continuous improvement of verification processes and toolchains.

Qualifications & Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.
• 5+ years of experience in software verification, preferably in test equipment or automation.
• Proficiency in C/C++, Python, and verification languages such as SystemVerilog or UVM.
• Strong understanding of digital and analog test concepts, signal integrity, and hardware interfaces.
• Experience with version‑control (Git), CI/CD pipelines, and automated testing frameworks.
• Excellent problem‑solving, communication, and teamwork skills.

Compensation & Benefits

Salary: $140,586.55 annually. Teradyne offers a comprehensive benefits package, including health insurance, retirement plans, paid time off, and professional development opportunities.

Location

North Reading, Middlesex County, United States.

Frequently Asked Questions

What does a Sr. Software Verification Engineer do at Teradaine?

They create and execute verification plans, develop automated test frameworks, collaborate with hardware teams, and ensure software quality for test and automation products.

What experience is required for this position?

At least 5 years of software verification experience, strong C/C++ and Python skills, and familiarity with verification languages such as SystemVerilog or UVM.

What is the salary for this role?

The position offers a fixed annual salary of $140,586.55.